Mehdi Modarressi

Mehdi Modarressi

modarressi (shift+2) ce.sharif.edu

modarressi (shift+2) ipm.ir

PhD Candidate

HPCAN (High-Performance Computing Architectures & Networks) Lab.
No. 701, Computer Engineering Department, Sharif University of Technology,

Azadi Ave., Tehran, Iran.

+98 (21) 66166672
&

Research Assistant

School of Computer Science, Institute for Studies in Fundamental Sciences (IPM),

Niavaran (Shahid Bahonar) Sq., Tehran, Iran.

+98 (21) 22287013 (2172)

I am currently a graduate student at Sharif University of Technology, pursuing a Ph.D. degree in Computer Engineering in the Department of Computer Engineering . My supervisor is Prof. Hamid Sarbazi-Azad and I am a member of the HPCAN (High Performance Computing Architectures and Networks) research group. I am also a research assistant in the IPM (Institute for Studies in Theoretical Physics and Mathematics, Now: Institute for Studies in Fundamental Sciences) school of computer science, Tehran, Iran.

At present, I am working on high-performance, low-power, and scalable dynamically reconfigurable network-on-chip (NoC) architectures. I lead a team of 7 M.Sc. students of our laboratory who work on different aspects of NoC design and optimization. I am involved in helping them in their projects and managing and supervising their respective tasks.

Last semester, Jan. 2010 to Sept. 2010, I was a visiting student with PARSA (Parallel Systems Architecture) Lab. at EPFL, Lausanne, Switzerland, directed by Professor Babak Falsafi.(My Page at EPFL).

Links:

Sharif University of Technology

Computer Engineering Department of Sharif U of Tech.

High Performance Computing Architectures and Networks (HPCAN) Lab. (Our Lab. Poster)

Institute for Studies in Theoretical Physics and Mathematics

Parallel Systems Architecture Laboratory (PARSA)

Ecole Plytechnique Federale de Lausanne (EPFL)

Education

. Ph.D. Student, Computer Engineering
Sharif University of Technology, Tehran, Iran : Since Sep. 2006.
Thesis: Using Reconfigurability to Improve the Power and Performance of Network-on-Chip Architectures
Supervisor: Prof. Hamid Sarbazi-Azad

. M.Sc., Computer Engineering
Sharif University of Technology, Tehran, Iran : Sep. 2003 - Jan. 2006 (1382-1384)
Thesis: Design and Implementation of an Object-Aware Cache for Object-Oriented Application Specific Instruction-Set Processors.
Supervisor: Prof. Shaahin Hessabi.

. B.Sc., Computer Engineering
Amirkabir University of Technology, Tehran, Iran: Sep. 1999 - Sep. 2003 (1378-1382)
Thesis: Implementing a Modem Compression Protocol (V44) in C and Optimizing the Code for the TMS320C6x Family DSP Processors.
Supervisor: Prof. Mehdi Sedighi

Research Experience

. Visiting Ph.D. Student (Dec. 2009-Sep. 2010)

PARSA Lab., Ecole Plytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland.

. Research Assistant (Sep. 2006- Now)

School of Computer Science, Institute for Studies in Fundamental Sciences (IPM), Tehran, Iran.

. Intern (Jul. 2003- Sep. 2003)

EDA Lab., Iran Telecommunication Research Center, Tehran, Iran.

Research Interests

. High Performance Computer Architectures.

. Network-on-Chips.

. Reconfigurable Computing Systems.

. Parallel Processing and Interconnection Networks.

. HDLs and Programmable Devices.

. Evolvable and Nature-Inspired Digital Systems.

. Scientific Computing and Computational Biology.

Teaching

Sharif University of Technology:

. CE40-232: Digital System Design: Fall 2011 [webpage at Sharif Courseware]

. CE40-534: VLSI design: Spring 2010 [webpage at Sharif Courseware]

. CE40-483: Hardware Description Languages: Fall 2008 [Course Web Page], Fall 2010 [webpage at Sharif Courseware]

. CE40-212: Logic Design: Spring 2009 [Course Web Page]

. CE40-333: Design and Co-design of Embedded Systems: Spring 2008 [Course Web Page]

. TA for CE40-103: Computer Architecture Lab., CE40-203: Logic Design Lab., CE40-206: Digital System Design Lab., CE40-506: Microprocessor Lab.

Tehran University:

. Microcontrollers: Spring 2011 [webpage at UT CECM]

. Interconnection Networks: Fall 2011 [webpage at UT CECM]

. Computer-Aided Design: Fall 2011 [webpage at UT CECM]

Publications

Journal Papers:

1. M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, "Application-Aware Topology Reconfiguration for On-Chip Networks", in IEEE Transactions on Very Large-scale Integrated Circuits and Systems (IEEE TVLSI), To be published.

2. M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, "VIP: Virtual Point-to-Point Connections in NoCs", in IEEE Transactions on Computer Aided Design for Integrated Circuits and Systems (IEEE TCAD), Vol. 29, No. 6, June 2010, pp. 5-18.

3. R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, "The 2D Digraph-Based NoCs: Efficient Alternatives to the 2D Mesh NoCs", in the Journal of Supercomputing, Springer, March 2010.

4. R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, "The 2D SEM: A novel high-performance and low-power mesh-based topology for networks-on-chip", International Journal of Parallel, Emergent, and Distributed Systems, Vol. 25, No. 4, August 2010, pp. 331-344.

Conference Papers:

5. M. Modarressi, H. Nikounia, A. H. Jahangir, "Low-power Arithmetic Unit for DSP Applications", in International Conference on System-on-Chip Design (SOC'11), Finland, Nov. 2011.

6. R. Jabbarvand, M. Modarressi, H. Sarbazi-Azad, "A Reconfigurable Fault-Tolerant Routing Algorithm to Optimize the Network-on-Chip Performance and Latency in Presence of Intermittent and Permanent Faults", in The 29th. International Conference on Computer Design (ICCD'11), USA, Oct. 2011.

7. H. Yaghoubi, M. Modarressi, H. Sarbazi-Azad, "A Distributed Task Migration Scheme for Mesh-based Chip-multiprocessors", in the 12th Conference on Parallel and Distributed Compilers, Architectures, and Technologies (PDCAT'11), South Korea, Oct. 2011.

8. M. Asadinai, M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, "Supporting Non-contiguous Processor Allocation in CMPs Using Virtual Point-to-point Links", in Design Automation and Test in Europe Conference (DATE'11), France, March 2011.

9. N. Teimouri, M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, "Energy-optimized On-chip Networks Using Reconfigurable Shortcut Paths", in the 23rd. Conference of Architectures for Computing Systems (ARCS'11), Italy, Feb. 2011.

10. M. Modarressi, H. Sarbazi-Azad, A. Tavakkol, "An Efficient Dynamically Reconfigurable On-Chip Network Architecture", in Design Automation Conference (DAC'10), USA, June 2010.

11. M. Asefi, M. Modarressi, H. Sarbazi-Azad, "A Load balanced Routing scheme for NoCs", in Workshop on MEMS (DMEMS'10), France, June 2010.

12. S. Sahhaf, M. Modarressi, H. Sarbazi-Azad, "A Novel SDM-based On-chip Communication Mechanism", in The Fourth European Conference of Modern Information and Communication Technologies (ECUMICT'10), Belgium, 2010.

13. M. Modarressi, H. Sarbazi-Azad, A. Tavakkol, "Low-power and High-Performance On-Chip Communication Using Virtual Point-to-Point Connections", in The IEEE/ACM International Symposium on Network-on-Chip (NoCS'09), USA, May 2009.

14. M. Modarressi, H. Sarbazi-Azad, M. Arjomand, "An SDM-Based Hybrid Packet-Circuit-Switched On-Chip Network", in Design, Automation, and Test in Europe Conference (DATE'09), France, April 2009.

15. R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, " The 2D DBM: An Attractive Alternative to the Simple 2D Mesh Topology for On-Chip Networks", in The 26th. International Conference on Computer Design (ICCD'08), USA, Oct. 2008.

16. M. Modarressi, H. Sarbazi-Azad, A. Tavakkol, "Virtual Point-to-Point Links in Packet-Switched NoCs", in IEEE Computer Society Symposium on VLSI (ISVLSI'08), France, May. 2008.

17. R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, "A Novel High-Performance and Low-Power Mesh-Based NoC", in The 7th. IPDPS Workshop on Performance Modeling, Evaluation, and Optimization of Ubiquitous Computing and Networked Systems (IPDPS'08 PMEO), USA, 2008.

18. M. Modarressi, H. Sarbazi-Azad, "Power-Aware Mapping for Reconfigurable NoC Architectures", in The 25th. International Conference on Computer Design (ICCD'07), USA, 2007.

19. S. Hessabi, M. Modarressi, M. Goudarzi, H. Javan-Hemmat, "A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems", in International Conference on Embedded Computing Systems: Architectures, MOdeling, and Simulation (IC-SAMOS VI), Greece, Jul. 2006.

20. M. Modarressi, S. Hessabi, M. Goudarzi, "A Reconfigurable Cache Architecture for Object-Oriented Application-Specific Processors", in Canadian Conference on Electrical and Computer Engineering (CCECE'06) , Canada, May 2006.

21. M. Modarressi, H. Javan-Hemmat, S.G. Miremadi, S. Hessabi, M. Najafvand, M. Goudarzi, M. Mohamadzadeh, "A Fault-Tolerant Approach to Embedded-System Design Using Software Standby Sparing", in The 11th. International CSI Computer Conference(CSICC'06), Iran, Feb. 2006, pp.77-84.

22. M. Modarressi, S. Hessabi, M. Goudarzi, "A Data Prefetching Mechanism for Object-Oriented Embedded Systems Using Run-Time Profiling", in The Third IEEE Symposium on Electronic Design, Test, and Applications (DELTA'06), Malaysia, Jan. 2006, pp.249-254.

23. M Modarresi, H. Sarbazi-Azad, "Parallel 3-Dimensional DCT Computation on k-Ary n-Cubes ", in The 8th International Conference on High Performance Computing in Asia Pacific Region (HPC-Asia 2005), China, Nov. 2005, pp.91-97.

24. M. Modarressi, M. Goudarzi, S. Hessabi, "Application-Specific Hardware-Driven Prefetching To Improve Data Cache Performance", in The Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC'05), Singapore, Oct. 2005, pp. 761-774.

Book Chapters:

25. M. Modarressi, H Sarbazi-Azad, "A High-Performance and Low-Power Reconfigurable Network-on-Chip Architecture", Chapter 13 in "Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication", published by IGI Global Pubs. (Amazon link)

26. R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, "Shuffle-Exchange Mesh Topology for Networks-on-Chip", Chapter 5 in Parallel and Distributed Computing (book title), IN-TECH Publishers, 2010. ISBN: 978-3-902613-45-5.

27. R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, "A Novel De Bruijn Based Mesh Topology for Networks-on-Chip", Chapter 16 in VLSI (book title), IN-TECH Publishers, 2010. ISBN 978-3-902613-50-9.

Other:

28. "Using Reconfigurability to Improve the Power and Performance of Network-on-Chip Architectures", Presented at ACM Student Research Competitions (ACM SRC) at PACT'10, Sept. 2010, Vienna, Austria (Silver Medal).

29. "A Low-Power and High-Performance Reconfigurable Network-on-Chip Architecture", Presented at DATE'09 PhD Forum, April 2009, Nice, France. (Poster)

My Publications in Persian Journals and Conferences

Honors

. Silver medal in ACM Student Research Competition (ACM SRC) at PACT'10, Vienna, Austria, Sept. 2010.

. Ranked 1st. in Computer Engineering Ph.D. Entrance Exam., Sharif University of Technology, 2006.

. Ranked 2nd. Among B.S. Program Students, Computer Engineering (Hardware), Amirkabir University of Technology, 2003.

My PhD Research

. Abstract of My PhD Research Proposal

. My Poster of ACM SRC at PACT'10

. My Poster of DATE'09 PhD Forum

. My Thesis in the News!

. Interview with Sharif University Daily Newspaper as the distinguished young researcher of Computer Engineering Department, Sept.15, 2009, page 8.

. Interview with Radio Javan as a distinguished young researcher of Sharif University, Aug. 25, 2009.

. News about my research project: IRNA, ISNA.